FIG. 1 shows a prior art computing system architecture. According to the architecture of FIG. 1, a memory controller 101 is responsible for presenting data in system memory 102 to both one or more processors 103 and a display controller 104. The particular memory controller 101 observed in FIG. 1 also includes one or more graphics controllers 116, a front side bus interface 107, a system memory interface 106 and core logic 108. The front side bus interface 107 has logic circuitry that controls the memory controller's signaling between the processor(s) 103. The system memory interface 106 has logic circuitry that controls the memory controller's signaling between system memory 111.
The system memory interface 106 is coupled to the system memory 102 with a data bus wiring 110 and memory clock (I/O_MCLK) wiring 111. The memory clock signal that appears on the memory clock wiring 111 is provided by the memory controller 101 and is used to control the rate at which operations are performed by the system memory 102. The memory clock signal is taken directly (or derived from) an output of Memory Interface Clock (MIC) circuitry 109. In an implementation, the MIC circuitry 109 is implemented as a delay locked loop (DLL) that imposes precise delay between a reference clock (not shown in FIG. 1) and one or more output clocks.
The front side bus interface 107 is coupled to the processor(s) 103 by front side bus wiring that carries transactions (e.g., for reads/writes from/to system memory 102) between the memory controller 101 and the processor(s) 103. The memory controller's core logic 108 includes logic circuitry that performs the memory controller's “core” function, namely, responding to requests to read/write data from/to system memory 101 that are sent by the processor(s) 103, the graphics controller(s) 116, the display controller 104 and perhaps one or more “I/O devices” (e.g., a disk drive, a network interface, a bus for attachment to a peripheral device (e.g., a printer) such as the Universal Serial Bus (USB), etc.).
Both the front side bus interface 107, the graphics controller(s) (not shown) and the core logic 108 of the memory controller 101 are clocked by Memory Controller Core (MCC) clock circuitry 112. In an implementation, the MCC clock circuitry is implemented as a phase locked loop (PLL) that “multiplies up” the frequency of a reference clock. The reference clock of the MCC clock circuitry 112 and the reference clock of the MIC circuitry 109 are typically different such that the memory controller 101 has both a “core side” clock domain and a “memory side” clock domain.
The display controller 104 is coupled to the memory controller (typically, through a “display port” interface designed into the memory controller 101 that has not been drawn in FIG. 1 for illustrative convenience). The display controller 104 includes a first, “display” FIFO 113 that stores data that was read from system memory 102 and that will be processed by the display controller's core logic 114 so that it can ultimately be rendered on the display 105 (such as a “flat panel” display (e.g., a thin film transistor (TFT) display)). The display controller's core logic 114 performs the “core” function of the display controller, namely, the processing of data so that it can be “rendered” on the display 105. The display controller 104 also includes a second “clock domain transition” FIFO 115 that permits the data produced by the display controller's core logic 114 to be driven toward the display 105 with a clock that is derived from a different source than the clock used to drive the display core logic 114. The display FIFO 113 fill rate is supposed to be no less than the display FIFO 113 empty rate. The display FIFO 113 empty rate requirement is determined by the display 105 configuration (e.g., display type, pixel resolution, and display refresh rate).
Prior art computing systems (and in particular mobile, battery operated computing systems such as laptop and notebook computers) are designed so as to operate according to different operational states that scale in both functional performance level and electrical power consumption. For instance, according to a “highest” performance and power consumption state (e.g., in which a processor is actively executing instructions), a processor will use its highest possible internal clock speed and will “activate” all of its internal circuitry regions. In a lower performance and power consumption state (e.g., in which a processor is “idling”), the processor will use a lower internal clock speed and may even have certain regions of its circuitry “deactivated”. In an even lower performance and power consumption state (e.g., in which a processor is “hibernated” or “sleeping”), the processor reduces to a lowest possible internal clock speed and deactivates significant portions of its internal circuitry.
The system memory 101 can also scale performance and electrical power consumption in order to support the computing system's various performance and power scaled operational states. For instance, system memory 101 may have a higher “auto-refresh” performance and power consumption state in which the system memory 101 needs an active memory clock 111 signal in order to prevent it from losing its internally stored data. The system memory 101 may also have a lower “self refresh” performance and power consumption state in which the system memory 101 does not need an active memory clock 111 signal in order to prevent it from losing its internally stored data.
The display 105, when illuminated with content, also needs to be continuously “refreshed” with data to be displayed. Here, the operation of rendering content on a display 105 can be viewed as the repeated displaying of a “screen's worth” of data. The screen's worth of data may change from screen view to screen view in order to effect visual changes in the matter that appears on the display 105 (and/or, the screen's worth of data may not change, but, still needs to be provided to the display 205 because displays are generally designed so that their visual content will degrade in appearance if they are not resent “new data” that corresponds to the same, continuously displayed imagery). At least when “new content” is continuously being presented on the display 105, the memory controller 101 may need to continuously read new data from system memory 101 and present it to the display controller 104 (which enters it into the display FIFO 113) at a rate high enough to prevent FIFOs 113 and 115 from starving. Note that the data being read from system memory 102 may previously have been processed by the graphics controller(s) (not shown) and written into system memory 102.
An operational mode of the memory controller 101 and display controller 104, referred to as “display mode” (because the display controller 104 is essentially given a sufficiently high bandwidth connection through the memory controller 101 to the system memory 102), is used to support the continuous (“streaming”) presentation of new content on the display 105. It is moreover possible that, while the memory controller 101 and display controller 104 are in the display mode, the processor(s) 103 are in a reduced performance and power consumption state in which requests will not be presented to the memory controller 101 over the front side bus for reads/writes from/to system memory 102. Here, the display 105 should be kept updated even if the processor(s) 103 are in a low performance and power consumption mode (such as no clocks, or very low frequency clocks, running, and/or many functional blocks disabled)
Unfortunately, the memory controller 101 and display controller 104 of the prior art computing system of FIG. 1 were not specifically designed to substantially reduce the power consumption of the computing system's integrated graphics mode when the memory controller's front side bus was essentially inactive. Specifically, the MCC clock 112 was “always on” which essentially caused the memory controller's graphics controller(s) and core logic circuitry 108 as well as the display controller's display FIFO 113 (and perhaps parts its core logic 114) to continuously consume electrical power.